This invention relates to the field of printed feature manufacturing, such as printed circuit boards and integrated circuitry manufacturing. In particular, this invention relates design tools for printed circuit board layouts and integrated device layouts. More specifically, the invention relates to graphically identifying each violation of a design rule to a user using the output of a design rule checker.
Computer aided design (CAD) software programs are used to create design drawings such as electrical schematics. To fabricate either a printed circuit board or an integrated circuit (IC), engineers first use a logical electronic design automation (EDA) tool, to create a schematic design, such as a schematic circuit design or layout. The layout typically contains data layers that correspond to the actual layers to be fabricated in the circuit board or circuit. Such designs usually have to adhere to a set of predefined criteria, referred to as design rules, which are unique to the product, product type, or manufacturing process. Various techniques have been developed to ensure conformance to design rules. These techniques include the use of design rule checking programs run subsequent to the design creation and the use of interactive design rule checking procedures run continually during the design process.
Once the layout is created, the layout is verified to ensure that the layout has been properly executed and that the final layout created adheres to certain geometric design rules. These layout verifications are called design rule checks. Such tools are available from CADENCE DESIGN SYSTEMS and from MENTOR GRAPHICS. In these tools a number of physical design rule checkers exist. These rule checkers compare actual design data against a user or default-specified set of design parameters and output any non-complying features as violations. When anomalies or errors are discovered by these checking tools, the designer must repair the fault before the layout is sent out for circuit manufacturing and wafer fabrication. Design rule checking searches the design for violations of a predetermined set of conditions, for example, minimum line widths and minimum separations, and returns a result indicating whether design rule violations were found. The intermediate layer(s) associated with a design rule checker can store a list of design rule errors found, or a modified design that satisfies the design rules.
The design rule checker is typically a software program or module, which is provided by an established vendor or specially programmed. The design rule checker is adapted to receive a digital representation of the layout pattern to be analyzed. Such representations specify in a standard format the coordinates of defined edges on a pattern or other geometric features. Generally, the layout design is provided in a digital form to a design rule checker set to select only those features that violate the design rules. In U.S. Pat. No. 6,282,696 issued to Garza, et al., on Aug. 28, 2001, entitled “PERFORMING OPTICAL PROXIMITY CORRECTION WITH THE AID OF DESIGN RULE CHECKERS,” a design rule checker is used to locate features of an integrated circuit layout design meeting predefined criteria. A partial layout is created as a new file having coordinates for each small feature under consideration. However, graphical assistance in dealing with violations identified by the design rule checker is neither taught nor suggested.
One problem with these design rule checkers is that a majority of them output the violations as a text file. Reviewing the output of these design rule checkers requires significant time on the part of the user to locate and understand the violation by using the text output to manually interact with the design file. A few design rule checkers also output some graphical information, but in most cases this information is limited to a pointer that identifies a problem location without providing data related to any specifics about the violation. An example of this type of output is demonstrated by the CADENCE ALLEGRO™ DRC (design rule checker). In these types of systems, the location of the violation is given, but useful information concerning the violation remains unknown to the user.
In U.S. Pat. No. 6,415,421 issued to Anderson, et al., on Jul. 2, 2002, entitled “INTEGRATED VERIFICATION AND MANUFACTURABILITY TOOL,” a hierarchical database is taught to store shared design data accessed by multiple verification tool components, such as design rule check. The database includes representations of one or more additional, or intermediate layer structures that are created and used by the verification tool components for operations performed on the design being verified. Once again, however, graphical representations of violations are not suggested or taught.
Generally, the output of design rule checkers is a one-time-only output, either in a text file or in a view of the design file within the design environment. There are no utilities within the violation review process for a user to create a desired subset of those violations that could then be shared with a designer. The user is typically forced to manually edit the original text output and give the resulting list to the designer, who must repeat the process of manually locating and understanding the violations. Often, when reviewing a list of violations, the user needs to obtain more information about a particular violation, such as inquiring about the neighboring features or some of the properties associated with the violating feature. With traditional violation reviewing, the user enters a number of keystrokes to get this information. If in the process of obtaining this information, the view of the design changes significantly, such as scrolling to a different location within the design, manual effort is required to relocate the violation in question.
Consequently, there is a need in the art to take the output of a design rule checker and graphically identify each violation to the user using design tool operations.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a graphical method for viewing and editing output from a design rule checking system.
It is another object of the present invention to provide a system and method that takes a text file from a design rule checker and graphical displays violations to a user.
A further object of the invention is to provide an interactive graphic tool using the output of a design rule checker to allow multiple users to view output without re-running the rule checking software.
It is yet another object of the present invention to provide a non-destructive interactive graphical tool to allow a designer to work with design rule checking output without risking existing data.
Another object of the present invention is to allow a user to view a design violation from any rule-checking tool that outputs in compatible format.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.